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Zapytanie: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE OF COMPUTATIONAL METHODS IN SCIENC
Liczba odnalezionych rekordów: 16



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1/16
Nr opisu: 0000120869
A parallel algorithm for finding the shortest exit paths in mines.
[Aut.]: Tomasz* Jastrząb, Agata Buchcik.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 200013, bibliogr. 24 poz. (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

2/16
Nr opisu: 0000120880
A preface for Symposium No 29 "Logic Synthesis and Control Systems".
[Aut.]: Dariusz Kania, Józef Kulisz, R. Wiśniewski, G. Bazydło.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 120001 (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

3/16
Nr opisu: 0000120862
A technology mapping based on graph of excitations and outputs for finite state machines.
[Aut.]: Dariusz Kania, Józef Kulisz.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 120006, bibliogr. 13 poz. (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

FSM ; synteza logiczna ; partycjonowanie ; PLD ; odwzorowanie technologiczne

FSM ; logic synthesis ; partitioning ; PLD ; technology mapping

4/16
Nr opisu: 0000120851
Ethernet-based test stand for a CAN network.
[Aut.]: Adam Ziębiński, Rafał Cupek, Marek* Drewniak.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 120005, bibliogr. 14 poz. (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

ADAS ; elektronika samochodowa ; CAN ; CANoe

ADAS ; automotive electronics ; CAN ; CANoe ; test systems

5/16
Nr opisu: 0000120868
FPGA implementation of bit controller in double-tick architecture.
[Aut.]: Michał Kobyłecki, Dariusz Kania.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 120008, bibliogr. 9 poz. (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

FPGA ; implementacja sprzętu komputerowego ; sterownik logiczny ; synteza logiczna ; PLC ; logika programowalna

FPGA ; hardware implementation ; logic controller ; logic synthesis ; PLC ; programmable logic

6/16
Nr opisu: 0000120864
Methods for the design and analysis of power optimized finite-state machines using clock gating.
[Aut.]: Piotr Chodorowski.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 120007, bibliogr. 20 poz. (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

7/16
Nr opisu: 0000120881
Optimization of synthesis process directed at FPGA circuits with the usage of non-disjoint decomposition.
[Aut.]: Adam Opara, Marcin Kubica.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 120004, bibliogr. 12 poz. (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

BDD ; synteza logiczna ; dekompozycja nierozłączna

BDD ; logic synthesis ; non-disjoint decomposition

8/16
Nr opisu: 0000120863
Parallel induction of nondeterministic finite automata revisited.
[Aut.]: Tomasz* Jastrząb.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 200014, bibliogr. 14 poz. (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

9/16
Nr opisu: 0000120877
Review of advanced driver assistance systems (ADAS).
[Aut.]: Adam Ziębiński, Rafał Cupek, Damian Grzechca, Łukasz Chruszczyk.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 120002, bibliogr. 11 poz. (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

ADAS ; system bezpieczeństwa samochodowego ; połączenie danych ; unikanie wypadków drogowych

ADAS ; automotive safety system ; data fusion ; traffic accident avoidance ; radar and vision sensing

10/16
Nr opisu: 0000120879
Synthesis of energy-efficient FSMs implemented in PLD circuits.
[Aut.]: R. Nawrot, Józef Kulisz, Dariusz Kania.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2017, Thessaloniki, Greece, 21-25 April 2017. Eds. T. E. Simos, T. Monovasilis, Z. Kalogiratou. Melville : American Institute of Physics, 2017, art. no. 120003, bibliogr. 16 poz. (AIP Conference Proceedings ; vol. 1906, iss. 1 0094-243X)

automat skończony ; niski układ zasilania ; PLD ; pobór mocy ; układ synchroniczny

finite state machine ; low power circuit ; PLD ; power dissipation ; synchronous circuit

11/16
Nr opisu: 0000112477   
Binary tree-based low power state assignment algorithm.
[Aut.]: K. Kajstura, Dariusz Kania.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2016, Athens, Greece, 17-20 March 2016. Eds. Theodore E. Simos, Zacharoula Kalogiratou, Theodore Monovasilis. Melville : American Institute of Physics, 2016, 030007-1-030007-4, bibliogr. 10 poz. (AIP Conference Proceedings ; vol. 1790 0094-243X)

FSM ; kodowanie stanów ; niski układ zasilania ; układ sekwencyjny

FSM ; state assignment ; low power design ; sequential circuit

12/16
Nr opisu: 0000112473   
Decomposition synthesis strategy directed to FPGA with special MTBDD representation.
[Aut.]: Adam Opara, Marcin Kubica.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2016, Athens, Greece, 17-20 March 2016. Eds. Theodore E. Simos, Zacharoula Kalogiratou, Theodore Monovasilis. Melville : American Institute of Physics, 2016, 030008-1-030008-4, bibliogr. 11 poz. (AIP Conference Proceedings ; vol. 1790 0094-243X)

dekompozycja ; synteza logiczna

decomposition ; logic synthesis ; PMTBDD ; SMTBDD

13/16
Nr opisu: 0000112474   
Decomposition time effectiveness for various synthesis strategies dedicated to FPGA structures.
[Aut.]: Marcin Kubica, Dariusz Kania, Adam Opara.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2016, Athens, Greece, 17-20 March 2016. Eds. Theodore E. Simos, Zacharoula Kalogiratou, Theodore Monovasilis. Melville : American Institute of Physics, 2016, 030005-1-030005-4, bibliogr. 11 poz. (AIP Conference Proceedings ; vol. 1790 0094-243X)

synteza logiczna ; dekompozycja ; partycjonowanie ; FPGA

logic synthesis ; decomposition ; partitioning ; FPGA

14/16
Nr opisu: 0000112464   
Double-tick realization of binary control program.
[Aut.]: M. Kobylecki, Dariusz Kania.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2016, Athens, Greece, 17-20 March 2016. Eds. Theodore E. Simos, Zacharoula Kalogiratou, Theodore Monovasilis. Melville : American Institute of Physics, 2016, 030009-1-030009-4, bibliogr. 9 poz. (AIP Conference Proceedings ; vol. 1790, iss. 1 0094-243X)

sterownik logiczny ; PLC ; logika programowalna ; FPGA

logic controller ; PLC ; programmable logic ; FPGA

15/16
Nr opisu: 0000112468   
State assignment for asynchronous FSMs with the use of the incompatibility and complement graph.
[Aut.]: Józef Kulisz.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2016, Athens, Greece, 17-20 March 2016. $Eds. Theodore E. Simos, Zacharoula Kalogiratou, Theodore Monovasilis. Melville : American Institute of Physics, 2016, 030010-1-030010-4, bibliogr. 13 poz. (AIP Conference Proceedings ; vol. 1790 0094-243X)

asynchroniczne FSM ; synteza logiczna ; teoria grafów ; pokrycie ; problem komplementarności

asynchronous FSM ; logic synthesis ; graph theory ; covering ; complementarity problem

16/16
Nr opisu: 0000112465   
Synthesis of energy-efficient counters implemented in PLD circuits.
[Aut.]: Józef Kulisz, R. Nawrot, Dariusz Kania.
W: Proceedings of the International Conference of Computational Methods in Sciences and Engineering. ICCMSE 2016, Athens, Greece, 17-20 March 2016. $Eds. Theodore E. Simos, Zacharoula Kalogiratou, Theodore Monovasilis. Melville : American Institute of Physics, 2016, 030006-1-030006-4, bibliogr. 17 poz. (AIP Conference Proceedings ; vol. 1790 0094-243X)

obwód niskiego zasilania ; pobór mocy ; układ synchroniczny ; automat skończony ; PLD

low power circuit ; power dissipation ; synchronous circuit ; finite state machine ; PLD

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